CPU

ID: eac350d1-fecc-4b02-a933-acd6121789a8
CREATED: <2025-06-09 Mon 13:35>

[2025-06-09 Mon 13:37] – Zen 4 - Microarchitectures - AMD - WikiChip [2025-06-09 Mon 13:44] <- 9004 [2025-06-09 Mon 17:12] – wiki

Zen 4 introduced the following ISA enhancements:

AVX-512 - 512-bit Vector Instructions AVX512F - Foundation (first introduced with Intel Skylake) AVX512CD - Conflict Detection Instructions (Skylake X) AVX512VL - Vector Length Extensions (Skylake X) AVX512DQ - Doubleword and Quadword Instructions (Skylake X) AVX512BW - Byte and Word Instructions (Skylake X) AVX512_IFMA - Integer Fused Multiply-Add (Cannon Lake) AVX512_VBMI - Vector Bit Manipulation Instructions (Cannon Lake) AVX512_VPOPCNTDQ - Vector Population Count Instructions (Ice Lake) AVX512_BITALG - Bit Algorithms (Ice Lake) AVX512_VBMI2 - Vector Bit Manipulation Instructions 2 (Ice Lake) AVX512_VNNI - Vector Neural Network Instructions (Ice Lake) AVX512_BF16 - BFloat16 Instructions (Cooper Lake) Not supported: AVX512ER, AVX512PF (Knights Landing); AVX512 4VNNIW, 4FMAPS (Knights Mill); VP2INTERSECT (Tiger Lake); FP16 (Sapphire Rapids) GFNI - Galois Field New Instructions (first introduced with Intel Ice Lake) VGF2P8AFFINEQB - Galois field affine transformation VGF2P8AFFINEINVQB - Galois field affine transformation inverse VGF2P8MULB - Galois field multiply bytes

• chips and cheese - AMD's Zen 4

ID: 275c4cf2-2703-4261-a3c1-49720e9a61e4
CREATED: <2025-06-09 Mon 13:35>

[2025-06-09 Mon 13:37] – Zen 5 - Microarchitectures - AMD - WikiChip [2025-06-09 Mon 13:44] <- 9005 [2025-06-09 Mon 17:12] – wiki

ID: c88d5ce8-3348-4347-b85b-15cf4ef61e4f
CREATED: <2025-06-04 Wed 15:07>

[2025-06-04 Wed 15:07] – wiki