AMD

1.1. EPYC

ID: abec3188-a2e3-4abe-9b45-59985a6ca303
CREATED: <2025-06-09 Mon 13:36>

1. 9004
   

   ID: 812054ed-d108-43f5-bba7-e40f9604c0c8
   CREATED: <2025-06-09 Mon 13:36>
   

   [2025-06-09 Mon 13:44] -> Zen 4

   • Practical Strategies for Low-cost LLM Deployments Using 4th Gen AMD EPYC Processors
   • VM Migration Guide
2. 9005
   

   ID: 86c29a1a-359d-4049-816d-2ec56e6bdd5f
   CREATED: <2025-03-03 Mon 11:47>
   

   [2025-06-09 Mon 13:44] -> Zen 5

   • EPYC 9005 Architecture Overview

   • Core Complex (CCX)

     The term “Core Complex” refers to a set of cores sharing a last-level (L3) cache. An AMD EPYC 9005 CCX will either have up to eight Zen5 (classic) or sixteen Zen5c (dense) cores sharing a 32MB L3 cache. Enabling SMT allows a single CCX to support twice that number, i.e., 16 or 32 concurrent hardware threads.

   • Core Complex Die (CCD)

     Each Core Complex Die (CCD) of an AMD EPYC 9xx5 Series Processor contains a single CCX. Cores can potentially be disabled in BIOS using one or both of the following approaches:

     • Reduce the cores per CCD while keeping the number of CCDs constant. This approach increases the effective L3 cache per core ratio but reduces the number of cores sharing the L3 cache.

     • Reduce the number of active CCDs while keeping the cores per CCD constant. This approach maintains the advantages of cache sharing between the cores while maintaining the same cache per core ratio.